Small size MIPI interface LCD screen, fast response, simple design

   With the advent of the global 5G and AI intelligent era, the performance of CPU chips of hardware products has been greatly improved, and the requirements for LCD screen interfaces have also been increased. The demand for MIPI high-speed transmission interfaces is increasing. The LCD screens of MIPI interfaces have always been 3.5 inches or more. For high-resolution screens, there are no MIPI interface products on the market for small-sized screens below 3.5-inch LCD screens. After a long period of research and development and increased investment, our company has launched a variety of small-size MIPI interface LCD screens, including 2.0-inch MIPI interface and 2.4-inch MIPI interface, 2.8-inch MIPI interface, 3.0-inch MIPI interface, 3.2-inch MIPI interface LCD The screen is made of IPS material, which is much superior to the ready-made LCD screens on the market in terms of display effect, viewing angle and data transmission speed, so as to meet the needs of customers for small-sized MIPI interface LCD screens. These two products are now comparable to domestic And foreign customers in mass production supply.
   MIPI is specifically tailored for power-sensitive applications using low-amplitude signal swings in high-speed (data transfer) mode. Figure 2 compares the signal swing of MIPI with other differential techniques.
   Since MIPI uses differential signal transmission, the design needs to be strictly designed according to the general rules of differential design. The key is to achieve differential impedance matching. The MIPI protocol stipulates that the differential impedance value of the transmission line is 80-125 ohms.
   MIPI is specifically tailored for power-sensitive applications using low-amplitude signal swings in high-speed (data transfer) mode. Figure 2 compares the signal swing of MIPI with other differential techniques.
   Since MIPI uses differential signal transmission, the design needs to be strictly designed according to the general rules of differential design. The key is to achieve differential impedance matching. The MIPI protocol stipulates that the differential impedance value of the transmission line is 80-125 ohms.

Figure 2: Comparison of signal amplitudes for several popular differential-swing techniques

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  MIPI specifies a differential clock lane (lane) and a scalable data lane from 1 to 4, which can adjust the data rate according to the needs of the processor and peripherals. Moreover, the MIPI D-PHY specification only gives the data rate range, and does not specify a specific operating rate. In an application, the available data lanes and data rates are determined by the devices at both ends of the interface. However, the currently available MIPI D-PHY IP core can provide transfer rates up to 1 Gbps per data lane, which undoubtedly means that MIPI is well-suited for current and future high-performance applications.
   There is another big advantage of using MIPI as the data interface. MIPI is well suited for new smartphone and MID designs because the MIPI DSI and CSI-2 architectures bring flexibility to new designs and support compelling features such as XGA displays and greater than 8-megapixel cameras. With the bandwidth capabilities offered by new MIPI-enabled processor designs, novel features such as high-resolution dual-screen displays and/or dual cameras can now be considered utilizing a single MIPI interface.
    In designs that incorporate these capabilities, high-bandwidth analog switches designed and optimized for MIPI signals, such as Fairchild Semiconductor's FSA642, can be used to switch between multiple display or camera components. The FSA642 is a high-bandwidth triple differential single-pole double-throw (SPDT) analog switch capable of sharing one MIPI clock lane and two MIPI data lanes between two peripheral MIPI devices. Such switches can provide some additional advantages: isolation of stray signals (stubs) from non-selected devices, and increased routing and peripheral placement flexibility. To ensure the successful design of these physical switches on the MIPI interconnect path, in addition to bandwidth, some key switch parameters must be considered:

1. Off-isolation: In order to maintain the signal integrity of the active clock/data path, switches are required to have efficient off-isolation performance. For high-speed MIPI differential signals of 200mV with a maximum common-mode mismatch of 5mV, the off-isolation between switch paths should be -30dBm or better.

2. Differential delay difference: The delay difference (skew) between the internal signals of the differential pair (the delay difference within the differential pair) and the delay difference between the differential crossing points of the clock and data channels (the delay difference between channels) must be reduced to 50 ps or more Small. For these parameters, the industry's best-in-class differential delay performance for this class of switches is currently in the range of 20 ps to 30 ps.

3. Switch Impedance: The third major consideration when selecting an analog switch is the trade-off between the impedance characteristics of the on-resistance (RON) and on-capacitance (CON). The MIPI D-PHY link supports both low-power data transfer and high-speed data transfer modes. Therefore, the RON of the switch should be chosen in a balanced way to optimize the performance of mixed working modes. Ideally, this parameter should be set separately for each operating mode. Combining the best RON for each mode and keeping the switching CON low is very important to maintain the slew rate at the receiver. As a general rule, keeping CON below 10 pF will help avoid degradation (extension) of signal transition times through the switch in high speed mode.

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  Compared with the parallel port, the module of MIPI interface has the advantages of fast speed, large amount of transmitted data, low power consumption, and good anti-interference. It is more and more favored by customers and is growing rapidly. For example, an 8M module with both MIPI and parallel port transmission requires at least 11 transmission lines and an output clock of up to 96M to achieve 12FPS full-pixel output; while using MIPI interface only requires 2 The frame rate of 12FPS under full pixel can be achieved with 6 transmission lines in the channel, and the current consumption will be about 20MA lower than that of parallel port transmission. Since MIPI uses differential signal transmission, the design needs to be strictly designed according to the general rules of differential design. The key is to achieve differential impedance matching. The MIPI protocol stipulates that the differential impedance value of the transmission line is 80-125 ohms.
  The figure above is a typical ideal differential design state. In order to ensure the differential impedance, the line width and line spacing should be carefully selected according to the software simulation; in order to take advantage of the differential line, the differential line pair should be tightly coupled inside, and the shape of the line should be symmetrical. Even the positions of the via holes need to be placed symmetrically; the differential lines need to be equal in length to avoid transmission delays causing bit errors; in addition, it is important to note that in order to achieve tight coupling, do not use the ground wire in the middle of the differential pair, and the definition of the PIN is also the best Avoid placing ground pads between differential pairs (referring to physically adjacent differential lines).
   The following briefly introduces the channel mode and online level of MIPI. In normal operation mode, the data channel is in high-speed mode or control mode. In high-speed mode, the channel state is differential 0 or 1, that is, when P in the line pair is higher than N, it is defined as 1, and when P is lower than N, it is defined as 0. At this time, the typical line voltage is differential 200MV, Please note that the image signal is only transmitted in high-speed mode; in the control mode, the typical amplitude of the high level is 1.2V. At this time, the signals on P and N are not differential signals but independent of each other. When P is 1.2V, N When it is also 1.2V, the MIPI protocol defines the state as LP11. Similarly, when P is 1.2V and N is 0V, the defined state is LP10, and so on. In the control mode, it can be composed of LP11, LP10, LP01, and LP00. Different states; the MIPI protocol stipulates that the different timings composed of four different states of the control mode represent entering or exiting the high-speed mode; for example, after the LP11-LP01-LP00 sequence, enter the high-speed mode. The figure below is an illustration of the line level.